Information may be transmitted isochronously over a Local Area Network ("LAN") or a Wide Area Network ("WAN"). FIG. 1 shows a system in which a computing node 42a is connected for audio, video, and data exchange (i.e., "customer information") over a WAN and with other, perhaps similar, computing nodes (e.g., node 42b). The computing node 42a is connected by an isochronous Ethernet serial physical layer link 47 to an isochronous-capable hub 40. Alternatively, the computing node 42 may be connected to a private branch exchange ("PBX"). The hub/PBX 40 is connected to a WAN, and backbone connections provide a connection from the hub/PBX 40 to other hubs/PBX's.
When information is transmitted isochronously, it is typically carried in one or more "B-channels". A B-channel, or "Bearer Channel", is a 64 kbits/sec channel that carries customer information such as voice-calls, circuit-switched data, or packet-switched data. A B-Channel has a constant, and thus predictable, bandwidth.
In a multi-channel isochronus network, one or more B-channel "logical streams" are time division multiplexed into a single higher speed channel to carry the customer information, but the information carried by one logical stream is typically unrelated to the information carried in another logical stream. For example, one logical stream may carry video information while another logical stream may carry audio information. From a network perspective, when transferring customer information to a CPU in a computing node, it is desirable to ignore the logical stream divisions and buffer the information in the high speed channel on a frame-by-frame basis. However, since the logical streams are unrelated, it is desirable from the CPU point of view to see these logical streams as being held in separate, stand-alone, buffers.
Conventional network/CPU buffering circuits support "N" logical streams by utilizing "N" different hardware components to perform the buffering (i.e., one hardware component per logical stream). One disadvantage of the conventional network/CPU buffering circuits is that to support more than "N" logical streams, more hardware components must be provided. Conversely, it is inefficient to provide more than "N" hardware components to support less than "N" logical streams.